1. Field of the Invention
The present invention relates to a process for producing vertically insulated semiconductor areas having different thicknesses in an SOI (silicon-on-insulator) wafer, which has an insulating layer on which first active semiconductor areas with a first thickness are arranged in a layer of active semiconductor material.
2. Description of the Background Art
A process is known from U.S. Pat. No. 6,204,098, in which dielectrically insulated islands are produced on an SOI substrate. The insulated islands are filled by epitaxial growth. The active silicon layer of the SOI wafer serves as the seed. Only insulated islands of the same height can be produced by this means. An active layer within the islands has an initial, relatively large thickness. According to FIG. 6 of this publication, complementary MOS transistors are produced in the islands and vertical DMOS transistor cells outside the islands. The vertical DMOS transistor cells are flatter than the dielectrically isolated tubs. The vertical DMOS transistor cells are not dielectrically isolated from the substrate.
A structure is known from EP 1 049 156 A1 in which a trench structure (trench) is surrounded by oxide. The trench is filled by an ELO process (ELO=epitaxial lateral overgrowth) with use of a seed, which was produced in the bottom of the trench by opening the oxide layer. The seed opening is then closed by a trench. This is a costly and space-consuming structure.
BCDMOS technology (BCDMOS=bipolar-CMOS-DMOS) is generally understood to be integrated circuits and their manufacturing processes, in which high-voltage DMOS features are combined with low-voltage CMOS and bipolar properties on a chip. A voltage of five volts is a typical example of low voltage, whereas high voltage in this context is understood to be values of up to more than a hundred volts. DMOS transistors are used as high-voltage components, whereby the high voltage can be applied between the drain region and the source region of the transistor. For future concepts, it is absolutely necessary within the scope of BCDMOS technology to take into account the special requirements of both the CMOS area (low leakage current) and the DMOS area (high power, high dielectric strength, high heat dissipation). To avoid power losses in the CMOS portion (leakage current), to prevent parasitic capacitances, and thereby to improve among others the behavior of the transistors, layer thicknesses within the range of about 200 nm are necessary with silicon as the semiconductor material. This is contradicted, however, by the requirement of Smart Power components (on a DMOS basis) with a high voltage resistance and good heat dissipation. Both requirements lead to layer thicknesses that are clearly greater than the thickness of a micrometer.
In contrast to the bipolar technology, in MOS technologies there is a systematic approach to structure miniaturization by scaling of the length scale for component dimensions. Important electrical properties of MOS transistors do not depend on individual lengths, but rather on the ratios of transistor width and channel length. Based on this dependence, in principle all lengths and widths within a circuit can be reduced by a mutual scaling factor k, without a change in electrical properties.
The scale miniaturization of components in BCDMOS circuits with vertical SOI insulation, however, is limited by the aforementioned contradictory requirements. To minimize leakage currents at high temperatures, the active silicon thickness in the CMOS portion should be very thin, so that source and drain lie upon the buried oxide. In the DMOS drift region, the active silicon layer in contrast should be thicker to increase the dielectric strength.